The invention is directed to an incrementer for modifying an n-digit input binary number by one unit into an n-digit output binary number.
It is known to construct incrementers with carry-look-ahead technique, which use a two-stage logic (NAND-OR). This technique is particularly utilized for word widths up to four bits. Given greater word widths, gates having too many inputs would be required. The circuit is irregular since a different transfer function must be implemented for every bit of the input binary number (see IBM Technical Disclosure Bulletin, June 1985, pages 741 and 742 "MOSFET Look-Ahead Bit Incrementer/Decrementer").